1. Field of the Invention
The present invention relates to a configuration of a portion for reading of internal data in a semiconductor memory device. More particularly, the present invention relates to a sense amplifier circuit for internally amplifying data of a selected memory cell.
2. Description of the Background Art
FIG. 9 shows an exemplary configuration of a memory cell in a conventional static random access memory (SRAM). Referring to FIG. 9, the memory cell MC includes: a P channel MOS transistor (insulated gate type field effect transistor) MP01 connected between a power supply node and a storage node NDA and having its gate connected to a storage node NDB; a P channel MOS transistor MP02 connected between a power supply node and storage node NDB and having its gate connected to storage node NDA; an N channel MOS transistor MN03 connected between storage node NDA and a ground node and having its gate connected to storage node NDB; an N channel MOS transistor MN04 connected between storage node NDB and a ground node and having its gate connected to storage node NDA; an N channel MOS transistor MN05 rendered conductive selectively in response to a signal potential on a word line WL to connect storage node NDA to a bit line BL; and an N channel MOS transistor MN06 rendered conductive selectively in response to the signal potential on the word line WL to connect storage node NDB to a bit line /BL.
MOS transistors MP01 and MN03 constitute a CMOS inverter circuit, and MOS transistors MP02 and MN04 constitute another CMOS inverter circuit. These CMOS inverter circuits have their inputs and outputs cross-coupled to each other, thereby constituting a flip-flop. Storage nodes NDA and NDB latch data complementary with each other.
In access to memory cell MC (for data writing/reading), word line WL is driven to a selected state, and its voltage level attains an H level. In response, MOS transistors MN05 and MN06 are rendered conductive, and storage nodes NDA and NDB are connected to bit lines BL and /BL, respectively. In data reading, a voltage difference occurs between bit lines BL and /BL according to the voltages on storage nodes NDA and NDB. The voltage difference is sensed to be read in the data reading.
In data writing, complementary write data are transmitted to bit lines BL and /BL. The voltage levels of storage nodes NDA and NDB are set according to the write data.
In the configuration of SRAM cell MC shown in FIG. 9, load transistors MP01 and MP02 for retaining data of an H level are each formed, e.g., of a thin film transistor (TFT), which allows reduction in occupying area compared to the case where a pure resistance element is utilized for the load element. These load transistors (P channel MOS transistors) MP01 and MP02 have equivalent resistance values in the non-conductive states significantly greater than those in the conductive states. Thus, compared to the case where the pure resistance element is utilized as the load element, a through current and hence, current consumption during retaining data, can be reduced.
FIG. 10 schematically shows a configuration of a portion related to data reading in a conventional SRAM. Referring to FIG. 10, memory cells MC are arranged in rows and columns. Each memory cell MC has a configuration as shown in FIG. 9. Word lines WL0, WL1, . . . are placed corresponding to respective rows of memory cells MC, and bit line pairs BL0, /BL0; BL1, /BL1, . . . are placed corresponding to respective columns of memory cells MC. Bit line precharge/equalize circuits BPE0, BPE1 are provided for bit line pairs BL0 and /BL0, BL1 and /BL1, respectively, for precharging and equalizing the corresponding bit line pairs BL0 and /BL0; BL1 and /BL1 to a power supply voltage VDD level in response to a precharge/equalize instructing signal /BLEQ.
Column select gates CSG0, CSG1 are provided for bit line pairs BL0 and /BL0, BL1 and /BL1, respectively, which connect the corresponding bit line pair to an internal data line pair IOP according to column select signals on column select lines CSL0, CSL1, respectively. Column select gate CSG0 includes a CMOS transmission gate TX00 provided for bit line BL0 and a CMOS transmission gate TX01 provided for bit line /BL0, and is rendered conductive in response to the column select signal on column select line CSL0 and an output signal of an inverter IVa receiving this column select signal. Each of CMOS transmission gates TX00 and TX01 includes a P channel MOS transistor PQ and an N channel MOS transistor NQ that are connected in parallel with each other.
Column select gate CSG1 includes a CMOS transmission gate TX10 provided for bit line BL1 and a CMOS transmission gate TX11 provided for bit line /BL1, and is rendered conductive in response to the column select signal on column select line CSLL and an output signal of an inverter IVb receiving this column select signal.
One bit line pair is selected by the column select signals on the column select lines, and the selected bit line pair is connected via the corresponding column select gate to internal data line pair IOP.
For internal data line pair IOP, there are provided a data line precharge/equalize circuit IPE that is responsive to activation of precharge/equalize instructing signal /BLEQ for precharging and equalizing internal data line pair IOP to a power supply voltage level, and a sense amplifier 100 that is responsive to activation of a sense amplifier activating signal SAE for differentially amplifying the signals on internal data line pair IOP to generate internal read data Dout and /Dout. Specifically, sense amplifier 100, when activated, differentially amplifies a voltage difference, appearing on internal data line pair IOP, corresponding to data of a selected memory cell, and generates complementary internal read data Dout and /Dout. The detailed configuration of sense amplifier 100 will be described later.
In the SRAM shown in FIG. 10, in the stand-by state, bit line precharge/equalize circuits BPE0, BPE1, . . . and data line precharge/equalize circuit IPE are in an active state. Bite line pairs BL0, /BL0; /BL1, /BL1, . . . are held at a power supply voltage level, and internal data line pair IOP is precharged and equalized to the power supply voltage level.
When a data access cycle for data writing/reading starts, a word line corresponding to an addressed row is driven to a selected state, and storage data in the memory cells connected to the selected word line are read out to the corresponding bit line pairs. Memory cells MC each have a configuration as shown in FIG. 9, so that complementary data on bit lines BL and /BL are read out to the corresponding bit line pairs. In the data reading, bit line precharge/equalize circuits BPE0, BPE1, . . . are in an inactive state. Thus, voltage differences according to the storage data in the selected memory cells (memory cells connected to the selected word line) are generated in the respective bit line pairs.
Further, the column select line corresponding to an addressed column is driven to a selected state, and column select gate CSG connected to this selected column select line is rendered conductive. The bit line pair corresponding to the selected column is connected to internal data line pair IOP, and the voltage difference corresponding to the storage data in the selected memory cell is generated on this internal data line pair IOP. Here, data line precharge/equalize circuit IPE is already driven to an inactive state upon entering the access cycle.
Sense amplifier 100 differentially amplifies this voltage difference of internal data line pair IOP to generate internal read data Dout and /Dout.
FIG. 11 shows, by way of example, specific configurations of bit line precharge/equalize circuits BPE0, IPE and sense amplifier 100 shown in FIG. 10. In FIG. 11, one bit line pair BL#, /BL# is shown representatively.
Bit line precharge/equalize circuit BPE# provided for bit lines BL# and /BL# includes: precharging P channel MOS transistors PQ1 and PQ2 that are rendered conductive when precharge/equalize signal /BLEQ is activated (to an L level), and transmit a power supply voltage VDD to bit lines BL# and /BL# when made conductive; and an equalizing P channel MOS transistor PQ3 that is rendered conductive when precharge/equalize instructing signal /BLEQ is activated, and electrically short-circuits bit lines BL# and /BL# when rendered conductive.
Data line precharge/equalize circuit IPE includes: precharging P channel MOS transistors PQ4 and PQ5 that are rendered conductive, when precharge/equalize instructing signal /BLEQ is activated, to transmit power supply voltage VDD to respective internal nodes SAL and /SAL; and an equalizing P channel MOS transistor PQ6 that is rendered conductive, when precharge/equalize instructing signal /BLEQ is activated, to electrically short-circuits internal nodes SAL and /SAL. Internal nodes SAL and /SAL are connected to respective internal data lines of internal data line pair IOP shown in FIG. 10.
Bit lines BL# and /BL# are coupled to respective internal nodes SAL and /SAL via column select gate CSG#. Column select gate CSG# includes CMOS transmission gates TX#0 and TX#1 provided for bit lines BL# and /BL#, respectively. These CMOS transmission gates TX#0 and TX#1 are rendered conductive selectively in response to the column select signal on column select line CSL and an output signal of an inverter IV# receiving this column select signal.
Sense amplifier 100 includes: a P channel MOS transistor PQ7 connected between a power supply node and sense internal node SAN and having its gate connected to a sense internal node /SAN; a P channel MOS transistor PQ8 connected between a power supply node and sense internal node /SAN and having its gate connected to sense internal node SAN; an N channel MOS transistor NQ1 connected between sense internal node SAN and a node NDC and having its gate connected to sense internal node /SAN; an N channel MOS transistor NQ2 connected between sense internal node /SAN and node NDC and having its gate connected to sense internal node SAN; an N channel MOS transistor NQ3 connected between node NDC and a ground node and having its gate receiving sense amplifier activating signal SAE; an inverter IVc inverting a signal on sense internal node SAN to generate internal read data Dout; an inverter IVd inverting a signal on sense internal node /SAN to generate complementary internal read data /Dout; and P channel MOS transistors PQ9 and PQ10 that are rendered conductive, when sense amplifier activating signal SAE is inactivated, to connect internal nodes SAL and /SAL to sense internal nodes SAN and /SAN, respectively.
When sense amplifier activating signal SAE is in an inactive state, sense internal nodes SAN and /SAN in sense amplifier 100 are connected to internal nodes SAL and /SAL. When sense amplifier activating signal SAE is activated, MOS transistors PQ9 and PQ10 are rendered non-conductive, and sense internal nodes SAN and /SAN are isolated from internal nodes SAL and /SAL. MOS transistor NQ3 in sense amplifier 100 is rendered conductive in response to activation of sense activating signal SAE. In this state, i.e., in the state where charges are confined in sense internal nodes SAN and /SAN, sense internal nodes SAN and /SAN are driven according to their voltage levels.
Sense internal nodes SAN and /SAN are provided with stabilizing capacitors NCa and NCb, respectively, for stabilization of voltages of sense internal nodes SAN and /SAN. Now, the operation of the reading circuitry of the SRAM shown in FIG. 11 will be described with reference to operating signal waveforms in FIG. 12.
This SRAM is a clock synchronous type SRAM that operates in synchronization with a reference clock signal CLK. In this clock synchronous SRAM, a read command READ designating data reading is provided in synchronization with a rising edge of reference clock signal CLK. Read command READ is provided by setting a chip select signal /CS to an L level and a write enable signal /WE to an H level at a rising edge of reference clock signal CLK. An address signal is also supplied at the rising edge of reference clock CLK.
When read command READ is supplied, a control circuit (not shown) first drives precharge/equalize signal /BLEQ from an active state of an L level to an inactive state of an H level to cancel the internal equalized state. It then drives all the MOS transistors PQ1-PQ3 in bit line precharge/equalize circuit BPE# to an OFF state, and drives all the MOS transistors PQ4-PQ6 within data line precharge/equalize circuit IPE to an OFF state. The precharging operation of bit lines BL# and /BL# and internal data line pair IOP is completed when precharge/equalize instructing signal /BLEQ is inactivated.
According to the read command READ, the control circuit (not shown) takes in the address signal at a rising edge of reference clock signal CLK, decodes the address signal, and drives word line WL and column select line CSL corresponding to the addressed row and column to a selected state. In the memory cell MC connected to the selected word line WL, MOS transistors MN05 and MN06 shown in FIG. 9 are rendered conductive, and a voltage difference is produced between bit lines BL# and /BL# according to data stored in storage nodes NDA and NDB of the associated memory cell.
Column select gate CSG# is rendered conductive in response to the column select signal on column select line CSL, and bit lines BL# and /BL# corresponding to the addressed column are connected to internal nodes SAL and /SAL (internal data line pair IOP). In response, the voltages corresponding to memory cell data read out onto the associated bit lines BL# and /BL# are transmitted to internal nodes SAL and /SAL. The voltage differences between bit lines BL# and /BL# and between internal nodes SAL and /SAL (internal data line pair IOP) become a sufficient large voltage difference xcex94V after an elapse of a time Ta since the application of read command READ.
During the time Ta, sense amplifier activating signal SAE is in an inactive state of an L level, and MOS transistors PQ9 and PQ10 in sense amplifier 100, shown in FIG. 11, are in a conductive state. The voltage difference between internal nodes SAL and /SAL is transmitted to sense internal nodes SAN and /SAN, and thus, the voltage difference xcex94V corresponding to data of the selected memory cell on bit lines BL# and /BL# is transmitted to sense internal nodes SAN and /SAN. After an elapse of time Ts since application of the read command, this voltage difference of sense internal nodes SAN and /SAN becomes a sufficient large xcex94V, and sense amplifier activating signal SAE is driven to an H level. Responsively, MOS transistors PQ9 and PQ10 are rendered non-conductive and MOS transistor NQ3 is rendered conductive, so that sense amplifier 100 is activated to amplify the voltage difference of sense internal nodes SAN and /SAN.
When sense amplifier 100 is in an active state, MOS transistors PQ9 and PQ1 are kept non-conductive. Sense internal nodes SAN and /SAN are being isolated from bit lines BL#, /BL# and internal nodes SAL, /SAL (internal data line pair). Thus, sense amplifier 100 drives small capacitance of internal sense nodes SAN and /SAN to perform a fast amplifying operation, thereby generating internal read data Dout and /Dout.
When the sense operation is completed, sense amplifier activating signal SAE attains an L level, and selected word line WL and selected column select line CSL are driven to a non-selected state. MOS transistors MN05 and MN06 used in accessing memory cell MC are rendered nonconductive, and column select gate CSG# also becomes non-conductive. Precharge/equalize instructing signal /BLEQ attains an active state of an L level, and bit lines BL#, /BL# and internal data line pair IOP are again precharged and equalized to the power supply voltage level.
The SRAM memory cell is a flip-flop type memory cell, in which data reading is performed non-destructively, unlike the case of a DRAM (dynamic random access memory). Therefore, a restore operation of rewriting data read out from a memory cell to the memory cell becomes unnecessary, which reduces the cycle time, thereby enabling rapid access.
In sense amplifier 100, the sense operation is performed while the charges are being confined on sense internal nodes SAN and /SAN. Therefore, the load to be driven in the sense operation is small, which allows a fast sense operation, thereby enabling fast data reading.
With the configuration of the sense amplifier shown in FIG. 11, the sense operation is performed when sense amplifier activating signal SAE attains an H level, with the charges transmitted from bit lines BL# and /BL# being confined on sense internal nodes SAN and /SAN. However, these sense internal nodes SAN and /SAN are nodes within sense amplifier 100 and their capacitance is small. Therefore, these nodes are likely to fluctuate in potential when receiving noise due to coupling from adjacent circuits or other at the start of the sense operation, which increases the possibility of malfunction of sense amplifier 100.
As a countermeasure conventionally taken in order to suppress such influences of coupling noise and others on the charges confined in the sense internal nodes, as shown in FIG. 11, gate capacitors NCa and NCb, each formed of a MOS transistor, are connected to sense internal nodes SAN and /SAN, respectively, to provide a capacitance of a significant capacitance value, besides the interconnection line capacitance or parasitic capacitance such as junction capacitance of transistor, for increasing the capacitance values of the sense internal nodes /SAL and SAL, to enhance the noise immunity of sense internal nodes SAN and /SAN.
According to such countermeasure, such gate capacitors NCa and NCb, however, are required to be placed in the sense amplifier 100, and such requirement increases the layout area of the sense amplifier, and correspondingly, the chip manufacturing cost is increased due to the increase of the chip area.
Further, any amplifying circuit for internally transferring a small-amplitude signal will encounter the same problems as the sense amplifier as described above.
An object of the present invention is to provide an internal signal amplifying circuit improved in resistance to noise without increasing the layout area.
Another object of the present invention is to provide an internal data reading circuit with excellent noise immunity and a small occupying area.
A specific object of the present invention is to provide a semiconductor memory device including a sense amplifier circuit excellent in noise immunity and having a reduced layout area.
A semiconductor memory device according to an aspect of the present invention includes: an internal signal line for transmitting data of a selected memory cell; a sense amplifier activated, when a sense amplifier activating signal is activated, for amplifying a voltage of a sense internal node; and a charge confinement gate responsive to activation of an isolation control signal that differs from the sense amplifier activating signal, for isolating the internal signal line from the sense internal node.
A semiconductor memory device according to another aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; a sense amplifier commonly provided for the plurality of memory cells, for amplifying, when activated, data of a selected memory cell of the plurality of memory cells; a sense control circuit responsive to a reading operation instructing signal, for generating a sense amplifier activating signal to activate the sense amplifier; a confinement gate circuit provided corresponding to each column of the memory cells, for coupling, when made conductive, the corresponding column to an internal node of the sense amplifier; and a confinement control circuit responsive to the reading operation instructing signal and a column address signal, for setting the confinement gate provided corresponding to an addressed column to a conductive state for a prescribed period of time.
A semiconductor memory device according to a further aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; a sense amplifier commonly provided for the plurality of memory cells, for amplifying, when activated, data of a selected memory cell of the plurality of memory cells; a sense control circuit responsive to a reading operation instructing signal, for generating a sense amplifier activating signal to activate the sense amplifier; a column select gate responsive to a column select signal, for coupling an addressed column to an internal signal line; a confinement gate for coupling the internal signal line to an internal node of the sense amplifier when made conductive; and a confinement control circuit responsive to the reading operation instructing signal for setting the confinement gate to a conductive state for a prescribed period of time.
Preferably, the sense amplifier activating signal is activated before the confinement gate is rendered non-conductive.
The control signal for controlling the charge confinement gate of the sense amplifier and the sense amplifier activating signal for controlling activation/inactivation of the sense amplifier are provided separately. Accordingly, the charge confinement gate and the sense amplifier each can be activated at an optimum timing. Specifically, the sense amplifier can be activated at a timing at which the charges accumulated in the sense internal node are prevented from being affected by coupling noise or the like.
In particular, by activating the sense amplifier upon conduction of the charge confinement gate, the sense internal node is coupled to the selected memory cell column. Accordingly, the capacitance of the sense internal node becomes large, so that the influence of the noise can be suppressed.
One gate is utilized both for the column select gate and for the charge confinement gate. Thus, a transistor dedicated for charge confinement becomes unnecessary. This elimination reduces the number of transistors, and thus, the area occupied by the reading circuitry can be decreased.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.